Engineering, Sr Staff Engineer

Job title:

Engineering, Sr Staff Engineer

Company

Synopsys

Job description

Job Description and RequirementsSeeking a highly motivated and innovative FPGA engineer with strong theoretical and practical background in high-speed digital circuits and FPGA design. Candidate will be part of a team responsible for development of new technologies in a state of the art emulation systems. We are looking for a team-oriented, self-driven individual with a keen technical mind and an eye for detail. You will be expected to explore new technologies and techniques to enhance our current and future product lines.The position will expose you to customer challenges and debug. A robust methodology to handle complex situation and scenario is required for this role. Under the supervision of our Chief Architect you will become a top player and expert for our Hardware Assisted Verification product line.Responsibilities

• Design and RTL coding of high-speed digital circuits in FPGAs from concept to production.
• Defining detailed test plan and implementing Verilog simulation testcases to verify design functionality.
• Debug product, test and resolve design issues on hardware platforms
• Define hardware and firmware interfaces, protocols for circuits.
• Integration of IP cores Buses, DDR Controllers, PHYs, etc with other logic within FPGA
• Coordinate interoperability of digital modules with embedded software

Key Qualifications & Experience

• Proficient in Verilog, HDL language and FPGA design (Vivado, Quartus, etc)
• Knowledge of simulation and verification methodologies (VCS simulator, UVM/OVM).
• Proficient in FPGA timing closure/area optimization techniques
• Hands on Experience with bringup of FPGA designs
• Knowledge of ASIC and FPGA design flows is desirable.
• Excellent organization and communication skills for interacting between different design groups.
• Strong desire to learn and explore.
• Proficiency in C/C++ and scripting languages is a plus.

Minimum Requirements

• BS in EE or Computer Science, MS or PhD degree preferred
• Typically requires 10-12+ years of experience in ASIC/FPGA Development (Verilog, System Verilog and/or VHDL)

Systems Design GroupThe System Design Group strives to create disruptive, innovative system solutions built on our marketleading emulation, FPGA prototyping, virtual prototyping, verification IP, and optical design technologies for application areas including automotive, mobile, networking, and AI.About SynopsysAt Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.Stay Connected:Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.Hire TypeEmployeeJob CategoryEngineeringJob SubcategoryEngineering

Expected salary

Location

Rungis, Val-de-Marne

Job date

Sat, 22 Jun 2024 03:07:22 GMT

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