Senior Formal Verification Engineer

Job title:

Senior Formal Verification Engineer

Company

Apple

Job description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there’s no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product Do you have experience being at the center of a System-on-a-chip (SoC) design verification effort collaborating with design? Are you passionate about changing the world? We have a critical impact on getting high quality functional products to millions of customers quickly and we are hiring all levels from junior to senior roles.Description DescriptionAs a formal verification architect leading the complete formal verification for single or multiple design blocks and IP’s (CPU, Media IP, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.), you will be responsible for: Working with Apple’s world-class SOC and IP design engineers to develop a formal micro-architecture specification Developing comprehensive formal verification test plan Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture Crafting novel and creative solutions for verifying complex design micro- architectures Developing and implementing re-usable and optimized formal models and verification code base Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.Minimum Qualifications Minimum Qualifications

• Advanced knowledge of SoC/CPU/GPU designs, VLSI, and digital logic design and verification techniques
• Developed formal property proofs on industrial strength designs and architectures
• Deep understanding of pipeline architectures, memory/DMA controllers, out-of-order and speculative instruction execution hardware, bus interconnects, and cache coherence mechanisms
• Confirmed understanding of formal verification technologies/abstraction techniques
• Knowledge and experience in interpreting hardware specifications and using
• Temporal logic assertion-based languages such as SVA or PSL
• Experience in using EDA formal tools and tool development experience is a plus
• Proficiency in any scripting language with excellent debugging skills
• BS / MS / Ph.D in EE or CS is required

Key Qualifications Key QualificationsPreferred Qualifications Preferred Qualifications

• Extraordinary teammate with excellent interpersonal skills
• Passionate about developing world-class/innovative formal verification solutions

Education & Experience Education & Experience

Expected salary

Location

London

Job date

Thu, 31 Oct 2024 04:51:43 GMT

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