Senior HBM Product Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. 

HBM Design Technology Package Co-Optimization integrates across various teams to define, design and material specifications. Defining needed test vehicles and test requirements to enable advanced package development and further product qualifications. Segmenting and resolving chip/package interaction issues.

Micron HBM Design Technology Package Co-Optimization team is looking to hire an experienced semiconductor packaging Principal Engineer. Our Team’s Vision is to enable predictable delivery of industry leading HBM through defining requirements for design, technology and package to mitigate chip-package interactions.

(Disclaimer): While you may not exhibit all the characteristics/skills listed below today, we are highly interested in a teammate who is motivated to grow in technical breadth and depth. Suppose you are open to learning while being a valued member of a team of premier engineers. In that case, we are determined to help build upon your existing foundation, while rapidly growing your individual and collaborative skills in this exciting and outstanding opportunity. 

*This position will be a hybrid role located in Richardson, TX

*The seniority level offered will be based on a combination of experience and education. 

The responsibilities include:

• Data collection and analyses of AI workloads on HBMs in systems
• Analyses and synthesis of discrete and stacked DRAM/logic component data for package-level implications
• Qual issue segmentation and proposing mitigating options through synthesis of physical layout and associated relevant data
• Defining tests and test structures to evaluate chip package interactions

The requirements include

• Masters with >6 yrs experience or PhD in EE/Comp Sci with >3yrs experience
• Ability to analyze physical layouts and extract key features
• Experience with component testing, test modes and/or packaging flows
• Proficiency in data analyses and statistics
• Proficiency in Python
• Strong interpersonal and communication skills to be successful in a team-oriented collaborative work environment

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.  We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.  Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave.  Additionally, Micron benefits include a robust paid time-off program and paid holidays.  For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

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To learn more about Micron, please visit micron.com/careers

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